1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
2. Related Art
In recent years, with the high integration of a semiconductor integrated circuit, a semiconductor device that has a multilayered interconnect structure has been developed. In the semiconductor device that has the multilayered interconnect structure, a via is formed in order to connect interconnects formed in different wiring layers.
In recent years, when the semiconductor device is manufactured, a so-called dual damascene method has been widely used, in which an interconnect and a via are simultaneously formed.
Specifically, as shown in FIG. 6A, after forming an interconnect 802 in a lower insulating layer 801, an insulating interlayer 803 is formed, and a via hole 803A is formed in the insulating interlayer 803. Then, as shown in FIG. 6B, a first resist film 804 is formed on the insulating interlayer 803. Then, as shown in FIG. 6C, a second resist film 805 where an opening 805A according to the upper interconnect trench is formed is provided on the first resist film 804.
The first resist film 804 and the insulating interlayer 803 are etched in accordance with the opening 805A, and an interconnect trench 803D is formed. The interconnect trench 803D communicates with the via hole 803A.
The first resist film 804 and the second resist film 805 are removed by etching in the course of forming the interconnect trench 803D.
Next, a bottom portion of the via hole 803A of the interlayer insulting film 803 is removed. Next, as shown in FIG. 6D, the via hole 803A and the interconnect trench 803D are filled with a conductor to simultaneously form an upper interconnect 806 and a via 807.
In this manufacturing method, a deviation between the via hole 807 and the upper interconnect 806, that is, a positional deviation between the upper interconnect trench 803D and the via hole 803A becomes a problem. Accordingly, as shown in FIGS. 7A and 7B, separately from the via hole 803A, a position aligning groove 803B is formed in the insulating interlayer 803, and a position aligning opening 805B is formed in the second resist film 805 to form the interconnect trench 803D.
A positional relationship between the position aligning groove 803B of the insulating interlayer 803 and the via hole 803A and a positional relationship between a position aligning opening 805B of the second resist film 805 and an opening 805A according to a pattern of the interconnect trench are previously grasped.
For this reason, if a positional relationship between the position aligning groove 803B of the insulating interlayer 803 and the position aligning opening 805B of the second resist film 805 is grasped, it is possible to detect whether the via hole 803A and the opening 805A according to a pattern of the interconnect trench 803D exist at predetermined positions.
As a result, it is possible to prevent a deviation between a via 807 and an upper interconnect 806.    [Patent Document 1] Japanese Patent Application Laid-Open (JP-A) No. 2006-108571    [Patent Document 2] Japanese Patent Application Laid-Open No. 2001-160591
The present inventors have recognized as follows. In Japanese Patent Application Laid-Open (JP-A) No. 2006-108571, there are following problems.
As shown in FIG. 7B, in the manufacturing method according to the related art, after the second resist film 805 and the first resist film 804 are removed, the first resist film 804 may remain in the position aligning groove 803B.
As such, the remaining first resist film 804 causes a particle to be generated and causes manufacturing efficiency of the semiconductor device to be deteriorated.
Further, reference numeral 803C in FIG. 7B denotes an opening that is formed in accordance with the position aligning opening 805B of the second resist film 805.